This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present disclosure, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
The present disclosure relates generally to the field of semiconductor memories, and more particularly to memories used in programmable integrated circuits such as programmable logic devices (PLDs), which are commonly referred to as field programmable gate arrays (FPGAs).
As the name suggests, PLDs are electronic devices that may be programmed to perform a specific function or functions. FPGAs are one common type of PLD that use a grid of logic blocks that may be programmed to perform relatively advanced logic functions. FPGAs may be used in a wide variety of applications, including digital signal processing, computer hardware emulation, and high performance computing, for example. Indeed, FPGAs may find particular utility in telecommunications applications, consumer electronics, medical and test equipment, military applications, and industrial electronics. FPGAs are typically programmed or configured each time they are powered up, typically using a configuration memory. The configuration memory stores the programming for the FPGA and is typically random access memory, such as static random access memory (SRAM). As such, it is commonly referred to as configuration random access memory or “CRAM.”
Some of the challenges faced in designing CRAM include guaranteeing an acceptable write margin, read margin and leakage margin. Write margin refers to the ability of data line drivers to successfully overwrite the contents of each CRAM memory cell by driving the data line to logic “0” as the address line of the CRAM cell is asserted. Read margin refers to the ability for an address line transistor of the CRAM cell to pull-down the precharged data line (held high by the data line retainer) when the address line is asserted. Leakage margin refers to the ability of the data line retainer to keep the precharged data line held to logic “1” while the off-state address line transistors of all CRAM cells connected to that data line are leaking current during an off-state.
Historically, off-state leakage current was not large and, therefore, the leakage margin was not difficult to achieve. However, as the dimensions of the memory cells have decreased with advances such as 65 nm and 45 nm processing technologies, off-state leakage current has grown and, correspondingly, guaranteeing the leakage margin has become difficult. In particular, the larger leakage requires that the data line retainer be made stronger. However, if the data line retainer is made too strong, it becomes difficult for the CRAM memory cells to meet the read margin requirements. As smaller dimensions of the CRAM memory cells are achieved, guaranteeing read margin while at the same time guaranteeing leakage margins becomes even more difficult as the memory cells can possibly have worst-case local variation for read margin (meaning weak address transistor) while at the same time having worst-case local variation for leakage margin (meaning strong address transistor for higher off-state leakage). Traditionally, if meeting read margins did not allow a strong enough data line retainer to meet leakage margins, the only solution was to reduce the number of memory cells connected to each data line. This meant segmenting the data lines more often and adding more-frequent data line buffers, thus increasing the die area to be resolved.